20d ago
Layout Engineer
Broadcom·Technology
🏢On-site
|Yishun, SingaporeLayout Engineer
Broadcom | Technology
2 weeks agoOn-site
Full Time
Singapore, Yishun
Position:
Layout Engineer
Company:
Broadcom
Location:
Singapore, Yishun
Employment type:
Full time
Short Summary:
The Layout Engineer will be part of the Library Group within the Central Engineering Group, focusing on circuit design for memory, I/O, and Standard Cells.
Responsibilities:
- Understand and apply layout guidelines for standard cells, I/O memories, and new process rules.
- Schedule timeline and layout floor-planning.
- Complete quality layout and verification within planned schedule.
- Get up to speed quickly with new methodologies and communicate effectively with the library team.
Requirement:
- Strong layout knowledge with 3 to 4 years of experience.
- Skills in Cadence layout, Cadence schematic capture, CALIBRE & Hercules verification tools.
- Experience in submicron processes (e.g., 16nm, 7nm, 5nm, 3nm, 2nm, 1.4nm).
- Experienced in digital layout (standard cell, memory, I/O) and analog layout is a plus.
- Strong experience in memory layout design and physical verifications (LVS, DRC, ERC, Antenna, Electro Migration in CMOS process).
- Proficient in Cadence Layout tools VIRTUOSO and CALIBRE verification tools.
- Good experience in floor-planning, hierarchy layout, and chip integration.
- Knowledge of Script Programming and SKILL Programming is a plus.
- Ability to lead or train junior engineers and manage projects effectively.
Benefits:
Broadcom is an equal opportunity employer and considers qualified applicants without regard to various protected characteristics.
Layout Engineer
Company:
Broadcom
Location:
Singapore, Yishun
Employment type:
Full time
Short Summary:
The Layout Engineer will be part of the Library Group within the Central Engineering Group, focusing on circuit design for memory, I/O, and Standard Cells.
Responsibilities:
- Understand and apply layout guidelines for standard cells, I/O memories, and new process rules.
- Schedule timeline and layout floor-planning.
- Complete quality layout and verification within planned schedule.
- Get up to speed quickly with new methodologies and communicate effectively with the library team.
Requirement:
- Strong layout knowledge with 3 to 4 years of experience.
- Skills in Cadence layout, Cadence schematic capture, CALIBRE & Hercules verification tools.
- Experience in submicron processes (e.g., 16nm, 7nm, 5nm, 3nm, 2nm, 1.4nm).
- Experienced in digital layout (standard cell, memory, I/O) and analog layout is a plus.
- Strong experience in memory layout design and physical verifications (LVS, DRC, ERC, Antenna, Electro Migration in CMOS process).
- Proficient in Cadence Layout tools VIRTUOSO and CALIBRE verification tools.
- Good experience in floor-planning, hierarchy layout, and chip integration.
- Knowledge of Script Programming and SKILL Programming is a plus.
- Ability to lead or train junior engineers and manage projects effectively.
Benefits:
Broadcom is an equal opportunity employer and considers qualified applicants without regard to various protected characteristics.
Required Languages
🇬🇧 English