12d 16h ago
ASIC Design Engineer
Tensordyne·General · Artificial Intelligence
🏢Hybrid
|Sunnyvale, United States of AmericaASIC Design Engineer
Tensordyne | General | Artificial Intelligence
Hybrid
Full Time
United States of America, Sunnyvale, Munich
Source not independently verified
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Position:
Mid Level ASIC Design Engineer
Company:
Tensordyne
Location:
(Country: USA, City: Sunnyvale)
Employment type:
Full Time
Work Arrangement:
Onsite
Short Summary:
As a member of Tensordyne’s ASIC team, you will be responsible for the microarchitecture and design implementation of a high-performance and low-power convolutional neural network accelerator ASIC for autonomous driving applications.
Responsibilities:
- Author/Understand micro-architecture specifications and participate in specification and test plan reviews.
- Implement complex RTL designs.
- Integrate CPU and other relevant IPs into the CPU sub-system.
- Collaborate with the physical design team to resolve implementation and timing issues and to optimize power.
- Analyze code coverage and provide feedback to the verification team to achieve coverage closure.
- Perform diagnostic and post-silicon validation tests, as well as assist with software bring-up in the lab.
Requirement:
- Requires 3+ years of ASIC RTL design experience with Verilog or SystemVerilog.
- CPU IP integration and Processor architecture knowledge.
- Familiarity with front-end ASIC tools and low-power design.
- Bachelor's degree in electrical or computer engineering (M.S. preferred).
Benefits:
- Comprehensive benefits and competitive compensation, including flexible spending and Bonusly awards.
- Commitment to a supportive and inspiring work environment.
Mid Level ASIC Design Engineer
Company:
Tensordyne
Location:
(Country: USA, City: Sunnyvale)
Employment type:
Full Time
Work Arrangement:
Onsite
Short Summary:
As a member of Tensordyne’s ASIC team, you will be responsible for the microarchitecture and design implementation of a high-performance and low-power convolutional neural network accelerator ASIC for autonomous driving applications.
Responsibilities:
- Author/Understand micro-architecture specifications and participate in specification and test plan reviews.
- Implement complex RTL designs.
- Integrate CPU and other relevant IPs into the CPU sub-system.
- Collaborate with the physical design team to resolve implementation and timing issues and to optimize power.
- Analyze code coverage and provide feedback to the verification team to achieve coverage closure.
- Perform diagnostic and post-silicon validation tests, as well as assist with software bring-up in the lab.
Requirement:
- Requires 3+ years of ASIC RTL design experience with Verilog or SystemVerilog.
- CPU IP integration and Processor architecture knowledge.
- Familiarity with front-end ASIC tools and low-power design.
- Bachelor's degree in electrical or computer engineering (M.S. preferred).
Benefits:
- Comprehensive benefits and competitive compensation, including flexible spending and Bonusly awards.
- Commitment to a supportive and inspiring work environment.
Required Languages
🇬🇧 English
Key competency: General