Principal Embedded Software Architect (Top Secret Clearance Required)

Title: Principal Embedded Software Architect (Top Secret Clearance Required) Location: Arlington, VA

Principal Embedded Software Architect

The Systems Development Division (SDD) delivers technology advantage into users’ hands by delivering capabilities focused on end-customer needs that function in operationally relevant environments and timeframes. SDD considers the entire lifecycle of the solution, from conceptualization and architecting, through development, to deployment, while leveraging novel technologies to deliver first-of-a-kind systems. Current efforts include programs for airborne and space RF as well as advanced testing enabled by multi-function, multi-modal capabilities.

STR is seeking a Principal Embedded Software Architect to define and lead the embedded software architecture for advanced RF systems, including software-defined radios, digital receivers/exciters, and radar subsystems built around MPSoC platforms. You will work hands-on in C/C++ and embedded Linux while providing technical leadership across a multidisciplinary team spanning FPGA, RF, digital hardware, and systems engineering.

In this role, you will own the embedded software stack that integrates high-speed data converters, FPGAs, and multi-core processors, with emphasis on data acquisition, streaming, timing, and deterministic control. You will drive system bring-up, integration, and test, ensuring that solutions meet performance, reliability, and maintainability requirements for operationally relevant environments.

What you will do

• Architect and lead development of embedded software for MPSoC-based RF systems (e.g., SDR, digital receivers/exciters, radar subsystems), from requirements through deployment.
• Define hardware/software partitions and interfaces; develop production-quality C/C++ and embedded Linux software (drivers, BSPs, low-level control, and application-level services).
• Bring up new boards and platforms in close collaboration with FPGA, RF, and hardware teams; configure and control high-speed ADCs/DACs, JESD links, and clocking/timing devices.
• Design, implement, and optimize data acquisition and streaming paths between FPGAs and processors, ensuring coherent timing, deterministic latency, and high-throughput operation.
• Lead system-level integration and test, including performance analysis, troubleshooting, and risk mitigation; prepare and maintain architecture documents, ICDs, and technical specifications.
• Provide technical leadership and mentorship to embedded and firmware engineers; lead design reviews, set development standards, and communicate status and technical decisions to stakeholders and customers.

Who you are

• This position requires an Active Top Secret security clearance, for which U.S. citizenship is needed by U.S. Government
• BS or Master’s in Computer Science, Electrical/Computer Engineering, Aerospace Engineering, or related field.
• Strong proficiency in embedded C/C++ for real-time, resource-constrained systems, and experience with embedded Linux (drivers, BSPs, kernel-level interfaces).
• Solid understanding of hardware/software interfaces (SPI, I2C, UART, GPIO, DMA, memory-mapped registers) and hands-on debugging using tools such as JTAG, logic analyzers, and oscilloscopes.
• Demonstrated experience architecting and integrating complex embedded systems involving MPSoCs/SoCs, FPGAs, and high-speed ADCs/DACs for RF or similar data-intensive applications.
• Proven technical leadership experience: guiding multi-disciplinary teams, translating system requirements into embedded architectures, leading design reviews, and mentoring engineers.
• Background should include a BS and at least 8 years of applicable experience; or a Master’s and at least 5 years of applicable experience. Equivalent experience will be considered.

Nice to Haves

• Experience with AMD/Xilinx Zynq UltraScale+ MPSoC platforms and tools (Vivado, Vitis, PetaLinux).
• Practical experience with digital receiver/exciter systems, SDR, radar, phased arrays, or EW systems; familiarity with JESD204B/C, coherent multichannel timing, and clock distribution.
• Familiarity with DSP concepts relevant to embedded RF (DDC/DUC, filtering, beamforming, waveform generation) and radar/EW timing and synchronization.
• Experience with multithreaded programming, IPC, and synchronization in embedded Linux; familiarity with Yocto/Buildroot and high-throughput interfaces (PCIe, 10/25/100 GbE).
• Experience developing reusable embedded frameworks/HALs and leading full lifecycle development (requirements, architecture, implementation, integration, verification) for aerospace/defense or other high-reliability applications.

Pay Information
Full-Time Salary Range: $219,000 - $300,000

The salary range listed is based on external market data. Offers are based on factors, such as but not limited to, the candidate’s experience, education, training, key skills/critical skills, security clearances, and prevailing market and business conditions.