Senior Analog Layout Design Engineer

Position:
Senior Analog Layout Design Engineer

Company:
Weekday's Client

Compensation:
Rs 1500000 - Rs 3000000 (ie INR 15 - 30 LPA)

Location:
India, Bengaluru

Employment type:
Full-time

Work Arrangement:
On-site

Short Summary:
We are looking for a highly skilled Senior Analog Layout Design Engineer with 4–6 years of hands-on experience in analog and mixed-signal IC layout design. The ideal candidate will possess strong expertise in developing high-quality transistor-level layouts while ensuring compliance with advanced semiconductor process technologies and design methodologies.

Responsibilities:
- Design and implement transistor-level layouts for analog and mixed-signal integrated circuits including amplifiers, voltage regulators, PLLs, ADCs, DACs, LDOs, bandgap references, and other custom analog blocks.
- Develop optimized layouts that meet electrical performance, area, matching, noise, and reliability requirements.
- Perform layout verification using Design Rule Check (DRC) and Layout Versus Schematic (LVS) to ensure design correctness and manufacturability.
- Collaborate closely with circuit designers throughout the layout cycle to resolve layout-dependent effects and improve overall circuit performance.
- Optimize layouts for parasitic reduction, matching accuracy, electromigration, IR drop, and process variations.
- Execute floorplanning and block-level integration while maintaining design quality and schedule commitments.
- Participate in design reviews and provide technical recommendations to improve layout methodologies and best practices.
- Support tape-out activities and work with cross-functional teams to resolve physical verification issues.
- Maintain layout documentation and adhere to company design standards and process guidelines.

Requirement:
- Bachelor's or Master's degree in Electronics, Electrical Engineering, Microelectronics, VLSI Design, or a related discipline.
- 4–6 years of professional experience in analog or mixed-signal layout design.
- Proven experience working on full custom layout development through successful tape-outs.
- Strong hands-on experience in Analog Layout design for custom IC development.
- Excellent knowledge of DRC and resolving design rule violations.
- Proficiency in LVS verification and debugging layout mismatches.
- Strong understanding of device matching techniques, common centroid layouts, shielding, guard rings, symmetry, and routing strategies.
- Ability to interpret circuit schematics and translate them into optimized physical layouts.
- Strong analytical, debugging, and problem-solving abilities.
- Excellent communication and collaboration skills.

Benefits:
- Good-to-Have Skills: Experience performing PEX and analyzing extracted results.
- Hands-on experience with Cadence Virtuoso for custom layout development.
- Familiarity with Calibre for physical verification, DRC, LVS, and PEX flows.
- Exposure to FinFET or advanced process nodes is an added advantage.
- Knowledge of reliability checks including ERC, antenna checks, and electromigration analysis.