In this role, you will be building the digital part of the SEMRON’s future chip generations.
You will design, verify and optimize digital designs to meet our ambitious performance targets.
Design the digital part of SEMRON’s AI accelerator
Contribute to system architecture exploration efforts
Work closely with analog and software team to exchange requirements and implement them
Conduct power, performance and timing analysis
- In-depth knowledge in RTL design flow
- In-depth knowledge of modern microarchitectures, particularly those of AI accelerators.
- Good understanding of the capabilities and limitations of digital design tools.
- Good understanding in digital design trade-offs.
- Familiarity with low power design techniques.
- Experience with the Chisel HDL
- Experience in verification
- Experience with RISC-V
At SEMRON, we’re redefining what’s possible in AI hardware. Our core innovation lies in analog in-memory computing for deep neural network acceleration, enabling us to build compute architectures that scale vertically into the third dimension, much like NAND flash revolutionized memory. This leap in physical density allows us to deploy models with billions of parameters on chip areas as small as a few square millimeters.