Pre-Silicon Validation Engineer

Position:
Pre-Silicon Validation Engineer

Company:
Weekday's Client

Location:
India

Employment type:
Full-time

Short Summary:
This role is for one of Weekday's clients requiring a Pre-Silicon Validation Engineer with a minimum of 6 years of experience in ASIC/SoC emulation, pre-silicon validation, or verification.

Responsibilities:
- Strong hands-on experience with Cadence Palladium emulation platforms (XP, Z1, Z2, or Z3)
- Deep understanding of Palladium compilation/build flows, including advanced clocking, ICE (In-Circuit Emulation), and Virtual Interface (VIF) flows
- Good to have in RTL languages: Verilog, SystemVerilog, VHDL
- Strong programming skills in SystemC, C/C++ for transactor development and reference modeling
- Expertise in scripting languages: Python, TCL, Perl, and Shell
- Experience with debugging tools and debugger interfaces (Lauterbach, JTAG, Coresight/UltraSoC)
- Knowledge of SoC architectures (ARM/x86) and standard protocols: PCIe, DDR/LPDDR, AXI, USB, SPI

Requirement:
- 6+ years of experience in ASIC/SoC emulation, pre-silicon validation, or verification
- Must-have skills: Silicon Validation, Palladium, ASIC/SOC Emulation
- Good-to-have skills: Zebu, Veloce, Protium
- Experience with additional emulation platforms such as ZeBu, Veloce, or Protium
- Experience with FPGA prototyping (HAPS, Xilinx)
- UVM verification experience and simulation regression debug
- Experience with networking ASICs, Ethernet, RDMA, RoCE, or AI fabrics
- Exposure to firmware validation, embedded software bring-up