Physical Design Engineer

Position:
Physical Design Engineer (PNR)

Company:
Weekday's Client

Compensation:
Rs 1000000 - Rs 1500000 (INR 10 - 15 LPA)

Location:
India, Bengaluru

Employment type:
Full-time

Work Arrangement:
On-site

Short Summary:
We are looking for a talented Physical Design Engineer (PNR) with 2–6 years of experience in ASIC physical design to join our semiconductor engineering team. The ideal candidate should have hands-on expertise across the complete physical design flow, with strong proficiency in Floorplanning, Power Planning, Placement, Clock Tree Synthesis (CTS), and Place & Route (PNR).

Responsibilities:
- Execute complete Place & Route (PNR) flow for complex ASIC and SoC designs.
- Develop and optimize floorplans considering performance, congestion, power, and area constraints.
- Perform power planning, including power grid design, IR drop considerations, and power integrity optimization.
- Carry out standard cell placement with a focus on timing, congestion, and routability.
- Implement Clock Tree Synthesis (CTS) to achieve timing closure while minimizing clock skew and latency.
- Perform routing, design optimization, and engineering change orders (ECOs) to meet design objectives.
- Analyze and resolve timing violations across setup, hold, and signal integrity constraints.
- Collaborate with RTL, DFT, timing, and verification teams throughout the implementation cycle.
- Support physical verification activities including DRC, LVS, antenna, and electrical rule checks.
- Optimize designs for power, performance, and area (PPA) while ensuring high-quality implementation.
- Debug implementation issues and recommend improvements to enhance design efficiency and productivity.
- Maintain implementation documentation and participate in design reviews.

Requirement:
- Strong expertise in Place & Route (PNR) methodologies.
- Hands-on experience in Floorplanning for ASIC/SoC designs.
- Experience in Power Planning and power grid implementation.
- Proficiency in standard cell Placement optimization.
- Strong knowledge of Clock Tree Synthesis (CTS) and timing optimization.
- Good understanding of timing closure methodologies and static timing analysis concepts.
- Familiarity with physical verification and signoff requirements.
- Knowledge of advanced semiconductor design flows and physical design methodologies.
- Strong analytical and debugging skills with attention to design quality.
- Excellent communication and teamwork abilities.

Benefits:
- Opportunity to work on cutting-edge semiconductor products.
- Contributing to challenging design implementations and optimization activities.