Senior RTL Design Engineer

Position:
Senior SOC Clocks RTL Design Engineer

Company:
NVIDIA

Location:
Israel, Tel Aviv

Employment type:
Full time

Short Summary:
The NVIDIA System-On-Chip (SOC) group is looking for a Senior RTL Design Engineer to lead the development of clocking logic for next-generation networking chips. This role involves technical leadership in RTL design, guiding other engineers, and collaborating with various teams to ensure successful implementation.

Responsibilities:
- Act as the technical lead for SOC clocks development, overseeing implementation from specification through tape-out and bring-up.
- Collaborate with architecture and micro-architecture teams to define SOC clock and reset schemes.
- Write and review synthesizable Verilog/SystemVerilog RTL for clock generation and distribution.
- Mentor other RTL engineers, setting coding and quality standards.
- Work closely with the Physical Design team on clock tree implementation and timing constraints.
- Partner with Design Verification on clocking test plans and debug processes.
- Support software and firmware teams on clock programming sequences and low-power flows.
- Represent clocking implementation in cross-functional design reviews.

Requirement:
- B.Sc./M.Sc. in Electrical Engineering or Computer Engineering.
- 8+ years of relevant experience in RTL/logic design with multiple chips taken to tape-out.
- Demonstrated technical leadership and mentoring experience.
- Expert hands-on RTL design skills in Verilog/SystemVerilog.
- Deep understanding of clocking and reset design principles.
- Proficiency with design quality tooling and static timing analysis.
- Strong communication skills across various teams.

Benefits:
NVIDIA fosters a diverse and encouraging environment, committed to equal opportunity employment and valuing diversity in its workforce.