RTL Design Engineer

Position:
SOC Clocks RTL Design Engineer

Company:
NVIDIA

Location:
Israel, Tel Aviv / Israel, Beer Sheva / Israel, Yokneam

Employment type:
Full time

Short Summary:
The NVIDIA System-On-Chip (SOC) group is seeking a strong RTL Design Engineer to own the SOC clocking logic for next-generation networking chips, focusing on clock generation, distribution, and control logic.

Responsibilities:
- Owning the SOC clocking logic end to end: writing synthesizable Verilog/SystemVerilog RTL for clock generation, distribution, muxing, division, glitchless switching, gating, and reset synchronization.
- Defining and implementing the SOC clock and reset architecture with the micro-architecture team.
- Owning clock domain crossing infrastructure and CDC closure across the SOC.
- Partnering with the micro-architecture team to review specifications and provide feedback on design intent.
- Working with the Physical Design team on clock tree implementation and timing feedback.
- Supporting Software and firmware teams on clock programming sequences and low-power flows.
- Driving design quality through various checks and supporting SOC-level chip build and assembly.

Requirement:
- B.Sc./M.Sc. in Electrical Engineering or Computer Engineering.
- 3+ years of relevant experience in RTL/logic design.
- Solid hands-on RTL design skills in Verilog/SystemVerilog.
- Experience taking a design from micro-architecture specification through verification and physical implementation.
- Solid understanding of clocking and reset concepts.
- Familiarity with design quality tooling.
- Great teammate with strong communication skills.

Benefits:
NVIDIA is committed to fostering a diverse work environment and is proud to be an equal opportunity employer.