Verification Engineer

Project description

We are looking for a talented, detail-oriented, and motivated person. Your contributions will impact products that span the global x86 market from server to desktop and laptop designs.

Responsibilities

• * Develop and execute UVM-based verification environments for complex SoC/IP designs and ensure functional coverage and verification quality. * Verify system-level designs involving buses, memory controllers, bridges, and high-speed peripheral interfaces across different protocols. * Perform detailed waveform analysis, debug, and root-cause analysis using VCS, NCSIM, Verdi, ModelSim, and other simulation tools. * Collaborate with design, architecture, firmware, validation, and other cross-functional teams to resolve functional issues and drive verification closure. * Support ARM/RISC-V processor and boot-flow verification, leveraging C/assembly knowledge for software-driven and system-level validation

SKILLS

Must have

• * Experience 6-9y * Looking for an experienced ASIC Design Verification Engineer with 6+ years of experience and strong expertise in UVM-based verification methodology. * Strong understanding of system-level architecture, including AXI/AHB/CHI/ACE5 buses, bridges, memory controllers, and high-speed interfaces. * Experience with DDR4/DDR5, LPDDR4/LPDDR5, USB, PCIe Gen4/5/6, MIPI, I2C/I3C, SPI, and UART protocols. * Strong expertise in waveform debugging using industry-standard tools such as VCS, NCSIM, Verdi, and ModelSim. * Familiarity with ARM/RISC-V processors, boot flow, C/assembly, and strong cross-functional collaboration skills.

Nice to have

• Excellent written and verbal communication and presentation skills.