Validation Engineer

Project description

Looking for a Validation Engineer who can collaborate with teams and be available at the office every working day.

Responsibilities

• * Own test planning, execution, coverage, reporting and defect tracking for assigned Versal ACAP product areas. * Develop and execute system-level test scenarios from hardware configuration and board bring-up through bare-metal and OS-based software execution. * Perform hardware and simulation debugging, reproduce failures, identify root causes, report defects and verify fixes. * Collaborate with cross-functional and global teams across hardware, software, architecture and validation to understand requirements and drive verification closure. * Develop efficient verification methodologies and automation, prioritizing critical defect detection, coverage improvement, timely escalation and end-to-end project delivery.

SKILLS

Must have

• * Relevant experience of 2- 3 years * Responsible for verification and validation of next-generation Xilinx SoC-centric products, with a focus on Versal ACAP solutions. * Plan and execute end-to-end system validation, covering hardware configuration, software execution, and customer-focused usage scenarios. * Validate SoC solutions across bare-metal and OS-hosted environments, including Linux-based embedded systems. * Strong hands-on expertise in hardware, simulation, emulation and prototyping debug, with C/Assembly and embedded software knowledge. * Experience with Xilinx Vivado/IP Integrator, ARM/RISC architectures, FPGA flows, PCIe/SATA/USB, and Python/Perl/TCL/C-Shell scripting is preferred.

Nice to have

Top 3 skills: * Validation engineer * Understanding of SoC based s/w development and debug * Strong on-board debugging skills, understanding of emulation and prototyping platforms, Embedded C, Scripting - Python