Synthesis Engineer

Join Ericsson’s cutting-edge journey to shape the future of 5G networks! As an ASIC Synthesis Engineer, you’ll work on pioneering digital ASIC designs vital to Ericsson’s mobile network infrastructure. Our team, responsible for the final critical stage of chip design before fabrication, thrives on Lean and Agile principles, promoting close collaboration, daily progress-sharing, and continuous improvement. If you’re passionate about advanced technology and ready to make a meaningful impact in telecom, this role is crafted just for you. 

At Ericsson, we support your growth, offering opportunities to advance your skills while contributing to game-changing 5G/6G technologies. Here, you’ll find a supportive, innovative environment focused on quality, teamwork, and career development. Join us and help shape the future of telecom! 

• Engage in all backend development tasks, including synthesis, constraints development, equivalence checking, and place-and-route to deliver high-quality digital ASICs.
• Run Static Timing Analysis, timing sign-off, and optimize timing/area/power using Synopsys tools (Design Compiler, PrimeTime, ICC2/FC/Innovus).
• Work extensively with EDA tools and develop scripts (Python, TCL, Linux Shell) to automate processes and enhance project efficiency.
• Drive innovations in low-power design using UPF and provide input on physical implementation and floor planning.
• Collaborate with cross-functional teams in a supportive, knowledge-sharing environment, ensuring seamless integration and execution. 

• Expertise in backend development, specialising in synthesis, STA, and power optimisation in semiconductors. 5+ years of development experience through multiple successful ASIC tape-outs.
• Hands-on Knowledge and proficiency in EDA tools (Synopsys Design Compiler, Fusion Compiler, PrimeTime, ICC2/Innovus, Formality/LEC ) for timing, area, power closure on advanced technology nodes.
• Proficiency in scripting languages (Python, Perl, TCL, and Linux Shell) to automate and streamline workflows.
• Comfortable in UNIX/Linux environments, essential for efficient and effective backend operations.
• Commitment to Quality is a keen eye for detail and experience maintaining high standards in complex, high-impact projects.
• Extensive experience in low-power design techniques, including UPF application and VHDL/System Verilog for RTL2GDS flows.
• Looking for a skilled professional experienced in crafting timing constraints to effectively manage and control the timing aspects of complex design projects.
• A collaborative mindset with a strong focus on innovative solutions and continuous improvement in fast-paced environments.
• Solid communication skills, able to explain technical topics clearly and collaborate effectively across teams. 

Bonus Skills: 

• It is nice to have experience in leading technical teams and working with Multi/Many-Core CPU architectures. 
• Proficient in Clear Case, Git, and Synopsys tools like Spyglass, Design Compiler, and Formality for optimised backend development. 
• Familiarity with mobile communication standards, telecom, floor planning, and physical implementation to enhance ASIC design effectiveness.