Help us improve RVC
We use optional analytics cookies to understand how RVC is used. Allow analytics also enables a fully masked diagnostic recording on public vacancy pages. It stops before Apply and excludes page text, form fields, console, and network contents. We do not use advertising cookies. Cookie policy
RVC
JobsFor Employers
  1. Jobs
  2. /
  3. Senior Silicon Engineer

Senior Silicon Engineer

Clera | Semiconductors
1h 4m ago
On-site
Full Time
IC
United States of America
$200k - $300k USD/yr

About the Role

Lead silicon design for an AI accelerator, taking designs from FPGA prototypes through ASIC tapeout and bring-up. As a senior member of a small hardware team, you will shape technical direction across architecture, RTL, verification, and tooling, working closely with PCB, interconnect, software, and systems teams.

What You'll Do

  • Lead FPGA prototype development and optimization, from design specifications through deployment on working hardware.

  • Design and review synthesizable RTL for an ASIC, with a focus on clean microarchitecture.

  • Build and improve lint, simulation, synthesis, timing, and verification flows for rapid iteration and tapeout readiness.

  • Make architecture decisions across compute datapaths, memory systems, on-chip interconnect, and control logic.

  • Drive design through tapeout, bring-up, and delivery milestones, contributing hands-on during critical periods.

  • Mentor teammates and help grow the silicon engineering team.

What We're Looking For

  • At least 8 years of experience in digital design or silicon engineering, building RTL, FPGA prototypes, or ASICs.

  • Experience shipping synthesizable SystemVerilog or Verilog in production silicon or FPGA designs, and taking FPGA designs from RTL through synthesis, place-and-route, and deployment to working hardware.

  • Strong understanding of digital design, including pipelining, clocks, resets, latency, throughput, and microarchitecture.

  • Experience designing compute datapaths and memory systems with bandwidth and latency constraints.

  • Hands-on experience with simulation, linting, synthesis, SDC constraints, timing closure, and CDC verification.

  • Experience automating hardware flows with Python, Tcl, Make, Nix, or similar tools, plus background in AI accelerators or low-level AI kernels.

  • Tapeout experience, high-speed interfaces, formal verification, UVM, cocotb, firmware, or systems-level hardware drivers are valuable.

Compensation & Benefits

Base salary is $200,000 to $300,000 USD annually. Visa sponsorship is available.

Location

Full-time, on-site role in San Francisco, United States. This position is not remote or hybrid.

Required Skills

systemverilogverilogpythontclmake

Required Languages

🇬🇧 English

Related searches

  • Jobs in USA
  • Senior Jobs
1 jobs
Sort by
1h 4m ago

Senior Silicon Engineer

Clera·Semiconductors
$200k - $300k USD/yr
systemverilogverilogpythontclmake
🏢On-site
|United States of America
General
No similar jobs match these filters. Try changing or clearing a filter.
Popular job searches ▸
Roles
Python JobsJava JobsReact JobsTypeScript JobsGo JobsDevOps JobsNode.js JobsRemote C# and .NET JobsData Science JobsProduct Manager JobsDesign Jobs
Countries
United StatesUnited KingdomCanadaUS & EMEAGermanyPolandSpainNetherlandsPortugal
Experience
Senior JobsMid-Level JobsJunior Jobs
R© 2026 RVC Globalbuild d2d163eb
AboutJobs in Claude & ChatGPTPricingContactPrivacyCookiesRefundsTerms & ConditionsFor Employers