Position:
R&D Engineer IC Design 4
Company:
Broadcom
Compensation:
The annual base salary range for this position is USD 121,900.00 to USD 195,000.00.
Location:
USA-TX-Austin - River Place B7 / USA-CA San Jose Innovation Drive
Employment type:
Full time
Work Arrangement:
Not specified
Short Summary:
You will be responsible for the front end design and verification of design blocks for these cores, including architecture definition, logic design, synthesis, and design verification through simulation and formal verification.
Responsibilities:
- Design logic blocks from systems requirements documents
- Simulate and debug designs with Verilog simulation
- Work independently and as part of a large team spanning multiple geographies
Requirement:
- BS/MS in Electrical or Computer Engineering or equivalent
- Bachelors and 8+ years of related experience; or Masters degree and 6+ years of related experience
- Experience with complete ASIC or standard product implementation flow from RTL synthesis, timing analysis/closure
- Proficiency with design tools/flows: TCL/Perl scripting, Synopsys Design Compiler/DC topo or Cadence RTL compiler, Primetime for timing analysis, formal verification tools, Spyglass Lint, power analysis of RTL and gate level netlists, familiarity with DFT and scan methodology, version control (svn, git, etc)
Benefits:
- Medical, dental and vision plans
- 401(K) participation including company matching
- Employee Stock Purchase Program (ESPP)
- Employee Assistance Program (EAP)
- Company paid holidays, paid sick leave, and vacation time
- Paid Family Leave and other leaves of absence