18d 9h ago
Distinguished ASIC Design Engineer
Astera Labs·Semiconductors
🏢Hybrid
|Aachen, Germanyethernet
Distinguished ASIC Design Engineer
Astera Labs | Semiconductors
2 weeks agoHybrid
Full Time
Germany, Aachen
Source not independently verified — confirm the company domain before applying.
Position:
Distinguished ASIC Design Engineer
Company:
Astera Labs
Location:
Germany, Aachen
Employment type:
Full Time
Work Arrangement:
Onsite
Short Summary:
Astera Labs is building purpose-built silicon for rack-scale AI infrastructure. As a Distinguished Engineer, you will be a senior technical leader driving ASIC design for next-generation Ethernet and Scale-Up (ESUN) connectivity products.
Responsibilities:
- Define and drive ASIC architecture for Ethernet/ESUN connectivity products.
- Lead architecture and microarchitecture for high-performance Ethernet controllers, MACs, NIC datapaths, and AI interconnect fabrics.
- Solve complex scale-up networking challenges and mentor senior engineers.
- Drive execution from architecture through RTL, integration, verification, tapeout, and post-silicon bring-up.
Requirement:
- Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field.
- 15+ years of ASIC/SoC design experience with a track record of delivering complex, high-speed networking silicon.
- Deep expertise in RTL design and microarchitecture for high-performance networking ASICs.
- Strong understanding of RDMA architectures and transport protocols.
Benefits:
- We actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
Distinguished ASIC Design Engineer
Company:
Astera Labs
Location:
Germany, Aachen
Employment type:
Full Time
Work Arrangement:
Onsite
Short Summary:
Astera Labs is building purpose-built silicon for rack-scale AI infrastructure. As a Distinguished Engineer, you will be a senior technical leader driving ASIC design for next-generation Ethernet and Scale-Up (ESUN) connectivity products.
Responsibilities:
- Define and drive ASIC architecture for Ethernet/ESUN connectivity products.
- Lead architecture and microarchitecture for high-performance Ethernet controllers, MACs, NIC datapaths, and AI interconnect fabrics.
- Solve complex scale-up networking challenges and mentor senior engineers.
- Drive execution from architecture through RTL, integration, verification, tapeout, and post-silicon bring-up.
Requirement:
- Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field.
- 15+ years of ASIC/SoC design experience with a track record of delivering complex, high-speed networking silicon.
- Deep expertise in RTL design and microarchitecture for high-performance networking ASICs.
- Strong understanding of RDMA architectures and transport protocols.
Benefits:
- We actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
Required Skills
ethernet
Required Languages
🇬🇧 English