PHY Design Verification Engineer - Jobs - Careers at Apple
- Work closely with the system and design teams to review and understand the PHY subsystem microarchitecture, and create verification plans from specifications, review and refine to achieve coverage targets.
- Build block/subsystem level test benches with a reference model, using the best-in-class DV methodology. Architect test benches with maximum reusability in mind.
- Develop and execute both directed and constrained random tests, debug failures, manage bug tracking, and work with designers to drive closure of issues found.
- Create and analyze block/subsystem-level coverage models, and add test cases to increase coverage.
- Use machine learning and AI technologies to identify design and test bench issues and ensure DV quality.
- Support PHY subsystem validation using Palladium and/or FPGA.
- Work with team members to improve DV methodology and flow.
- BS and a minimum of 10 years relevant industry experience
- Verification experience of wireless/wired communication block/subsystem.
- Advanced knowledge of Verilog, SystemVerilog, UVM, and SystemVerilog Assertion.
- Excellent knowledge and experience of ASIC verification flows including test bench development, constrained random testing, and code/functional coverage.
- Experience of using Matlab/C reference model and bit-accurate verification.
- Verification experience of wireless/wired communication block/subsystem.
- Knowledge of wireless protocols such as Bluetooth, UWB, WLAN, or Zigbee.
- Proficient in shell and Python scripting, Perl scripting.
- Experience of using AI technologies in data mining/analysis.
- Experience of Palladium/FPGA validation.
- Should be a team player with excellent communication skills, self-motivated and well organized.
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🇬🇧 English