Lead Physical Design Engineer

Position:
Physical Design Engineer

Company:
Weekday's Client

Location:
India, Bengaluru

Employment type:
Full-time

Short Summary:
We are seeking an experienced Lead Physical Design Engineer to drive the complete ASIC physical design flow from RTL to GDSII. The ideal candidate will have strong expertise in synthesis, place and route (PNR), timing closure, signoff, and physical verification while leading a team of engineers on complex semiconductor projects.

Responsibilities:
- Lead the complete RTL-to-GDSII implementation flow for complex ASIC and SoC designs.
- Execute and oversee synthesis, floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and physical implementation.
- Drive design planning activities, including partitioning, macro placement, bump planning, and routing strategies.
- Optimize designs for timing, power, congestion, and area while achieving design closure.
- Perform physical verification and signoff, ensuring compliance with design and manufacturing requirements.
- Work closely with RTL, STA, DFT, Analog, and Verification teams to resolve implementation challenges.
- Integrate analog and mixed-signal IP blocks into digital designs while maintaining design quality.
- Develop and optimize power grids and support low-power implementation methodologies.
- Execute timing closure using ECO methodologies and optimize design performance.
- Perform signoff activities, including Logical Equivalence Check (LEC), Reliability Verification (RV), Layout Verification (LV), Static Timing Analysis (STA), power analysis, and low-power verification.
- Debug complex implementation and signoff issues to ensure successful tape-out.
- Lead, mentor, and manage a team of physical design engineers while driving project execution and delivery.
- Coordinate with cross-functional stakeholders to ensure project milestones and quality objectives are achieved.

Requirement:
- Strong experience in the complete RTL-to-GDSII physical design flow.
- Expertise in ASIC Physical Design, including synthesis and Place & Route (PNR).
- Hands-on experience with Fusion Compiler and/or Cadence Innovus.
- Strong knowledge of macro placement, floorplanning, power planning, placement, clock tree synthesis (CTS), and routing.
- Experience with design planning, partitioning, bump planning, and routing methodologies.
- Strong understanding of Static Timing Analysis (STA) and timing closure.
- Expertise in physical verification and signoff methodologies.
- Experience with LEC (Conformal), RV (Ansys), Layout Verification (Calibre DRC/LVS), PTPX, VCLP (VC Static Checks), and PrimeTime ECO/Tweaker.
- Experience implementing low-power designs and knowledge of ESD verification and signoff flows.
- Proven experience leading engineering teams of approximately 10 or more members.
- Experience integrating analog blocks into digital SoC designs.

Benefits:
- Strong technical leadership and mentoring abilities.
- Excellent analytical and debugging skills.
- Outstanding problem-solving capabilities.
- Strong communication and stakeholder management skills.
- Ability to manage multiple projects and priorities in a fast-paced environment.
- Collaborative mindset with experience working across cross-functional engineering teams.