Physical Design Engineer
- Location: Bengaluru (India)
- Work arrangement: on site
- Employment type: Full Time
- Seniority: middle
- Posted:
Job description
Position:
Physical Design Engineer
Company:
Weekday's Client
Location:
India, Bengaluru
Employment type:
Full-time
Short Summary:
We are seeking a talented Physical Design Engineer (PNR) to join our semiconductor engineering team. The ideal candidate will have hands-on experience in ASIC Physical Design, with expertise in Place & Route (PNR), floorplanning, power planning, and timing closure.
Responsibilities:
- Perform end-to-end ASIC Physical Design (Place & Route) implementation for complex chip designs.
- Execute physical design activities including floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and design closure.
- Optimize designs for timing, power, area, and congestion while ensuring implementation quality.
- Perform physical verification, design rule checks (DRC), and support engineering change orders (ECOs).
- Collaborate with RTL, STA, DFT, and verification teams to resolve implementation and timing-related issues.
- Analyze timing reports and implement fixes to achieve timing closure.
- Support low-power implementation and optimization methodologies.
- Work with physical design methodologies, automation, and best practices to improve implementation efficiency.
- Debug implementation issues and recommend design improvements to meet project goals.
- Contribute to continuous improvement of physical design flows and automation.
Requirement:
- 2–5 years of experience in ASIC Physical Design / Place & Route (PNR).
- Strong hands-on experience with Floorplanning.
- Expertise in Power Planning.
- Experience with Placement and physical optimization.
- Strong knowledge of Clock Tree Synthesis (CTS).
- Hands-on experience with Routing and routing optimization.
- Strong understanding of the complete ASIC physical design flow and timing closure.
- Experience using industry-standard EDA tools such as Cadence Innovus and/or Synopsys ICC2.
- Good understanding of physical verification, congestion analysis, and design optimization techniques.
Benefits:
- Strong analytical and debugging skills.
- Excellent problem-solving abilities with attention to detail.
- Good communication and collaboration skills.
- Ability to work effectively in cross-functional engineering teams.
- Self-motivated with the ability to manage multiple priorities in a fast-paced development environment.
- Strong commitment to quality, performance, and continuous learning.
Physical Design Engineer
Company:
Weekday's Client
Location:
India, Bengaluru
Employment type:
Full-time
Short Summary:
We are seeking a talented Physical Design Engineer (PNR) to join our semiconductor engineering team. The ideal candidate will have hands-on experience in ASIC Physical Design, with expertise in Place & Route (PNR), floorplanning, power planning, and timing closure.
Responsibilities:
- Perform end-to-end ASIC Physical Design (Place & Route) implementation for complex chip designs.
- Execute physical design activities including floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and design closure.
- Optimize designs for timing, power, area, and congestion while ensuring implementation quality.
- Perform physical verification, design rule checks (DRC), and support engineering change orders (ECOs).
- Collaborate with RTL, STA, DFT, and verification teams to resolve implementation and timing-related issues.
- Analyze timing reports and implement fixes to achieve timing closure.
- Support low-power implementation and optimization methodologies.
- Work with physical design methodologies, automation, and best practices to improve implementation efficiency.
- Debug implementation issues and recommend design improvements to meet project goals.
- Contribute to continuous improvement of physical design flows and automation.
Requirement:
- 2–5 years of experience in ASIC Physical Design / Place & Route (PNR).
- Strong hands-on experience with Floorplanning.
- Expertise in Power Planning.
- Experience with Placement and physical optimization.
- Strong knowledge of Clock Tree Synthesis (CTS).
- Hands-on experience with Routing and routing optimization.
- Strong understanding of the complete ASIC physical design flow and timing closure.
- Experience using industry-standard EDA tools such as Cadence Innovus and/or Synopsys ICC2.
- Good understanding of physical verification, congestion analysis, and design optimization techniques.
Benefits:
- Strong analytical and debugging skills.
- Excellent problem-solving abilities with attention to detail.
- Good communication and collaboration skills.
- Ability to work effectively in cross-functional engineering teams.
- Self-motivated with the ability to manage multiple priorities in a fast-paced development environment.
- Strong commitment to quality, performance, and continuous learning.
Skills
- perl
- python
Languages
EN
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