Design Verification Engineer
NXP Semiconductors · Semiconductors
- Location: Catania (Italy)
- Work arrangement: remote in country
- Employment type: Full Time
- Salary: €31.2k - €43k EUR/yr
- Seniority: middle
- Posted:
Job description
Position:
Junior Design Verification Engineer
Company:
NXP Semiconductors
Compensation:
Estimated gross annual base salary range for this position in Italy is between 31,200 € and 43,000 € annually.
Location:
Italy, Catania
Employment type:
Full time
Work Arrangement:
Not specified
Short Summary:
As a Design Verification Engineer at NXP Semiconductors, you will play a crucial role in ensuring the functional correctness and quality of our cutting-edge semiconductor designs. You will be responsible for developing and executing comprehensive verification plans to validate complex digital circuits.
Responsibilities:
- Develop and implement efficient and comprehensive verification environments and test benches using industry-standard methodologies (e.g., UVM, SystemVerilog).
- Create detailed verification plans based on design specifications, identifying key functionalities and potential corner cases.
- Develop, execute, and debug test cases to thoroughly verify the design against its specifications.
- Analyze simulation results, identify discrepancies, and work closely with design engineers to resolve issues.
- Develop and maintain verification collateral, including assertions, functional coverage models, and verification scripts.
- Participate in verification reviews, contributing to the improvement of verification methodologies and processes.
- Collaborate with design, architecture, and software teams throughout the product development lifecycle.
- Contribute to the continuous improvement of verification flows and tools.
- Document verification strategies, test plans, and results effectively.
Requirement:
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
- Proven experience (typically 2+ years) in digital IC design verification.
- Strong proficiency in SystemVerilog and UVM (Universal Verification Methodology).
- Experience with industry-standard simulation tools (e.g., Questa, VCS, Xcelium).
- Solid understanding of digital design principles and architectures.
- Experience with scripting languages such as Python, Perl, or Tcl.
- Familiarity with functional coverage driven verification and assertion-based verification.
- Excellent problem-solving skills and attention to detail.
- Strong communication and interpersonal skills, with the ability to work effectively in a team environment.
- Fluency in English, both written and spoken.
Benefits:
Not specified
Junior Design Verification Engineer
Company:
NXP Semiconductors
Compensation:
Estimated gross annual base salary range for this position in Italy is between 31,200 € and 43,000 € annually.
Location:
Italy, Catania
Employment type:
Full time
Work Arrangement:
Not specified
Short Summary:
As a Design Verification Engineer at NXP Semiconductors, you will play a crucial role in ensuring the functional correctness and quality of our cutting-edge semiconductor designs. You will be responsible for developing and executing comprehensive verification plans to validate complex digital circuits.
Responsibilities:
- Develop and implement efficient and comprehensive verification environments and test benches using industry-standard methodologies (e.g., UVM, SystemVerilog).
- Create detailed verification plans based on design specifications, identifying key functionalities and potential corner cases.
- Develop, execute, and debug test cases to thoroughly verify the design against its specifications.
- Analyze simulation results, identify discrepancies, and work closely with design engineers to resolve issues.
- Develop and maintain verification collateral, including assertions, functional coverage models, and verification scripts.
- Participate in verification reviews, contributing to the improvement of verification methodologies and processes.
- Collaborate with design, architecture, and software teams throughout the product development lifecycle.
- Contribute to the continuous improvement of verification flows and tools.
- Document verification strategies, test plans, and results effectively.
Requirement:
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
- Proven experience (typically 2+ years) in digital IC design verification.
- Strong proficiency in SystemVerilog and UVM (Universal Verification Methodology).
- Experience with industry-standard simulation tools (e.g., Questa, VCS, Xcelium).
- Solid understanding of digital design principles and architectures.
- Experience with scripting languages such as Python, Perl, or Tcl.
- Familiarity with functional coverage driven verification and assertion-based verification.
- Excellent problem-solving skills and attention to detail.
- Strong communication and interpersonal skills, with the ability to work effectively in a team environment.
- Fluency in English, both written and spoken.
Benefits:
Not specified
Skills
- perl
- python
Languages
EN
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