FPGA Timing Specialist
Digis · Software Development
- Work arrangement: fully remote
- Employment type: Full Time
- Seniority: senior
- Posted:
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Job description
Position:
Principal FPGA Timing Specialist
Company:
Digis (a Fiverr company)
Location:
Worldwide
Employment type:
Fulltime
Work Arrangement:
Full Remote
Short Summary:
We are looking for a Principal FPGA Timing Specialist to analyse and optimise existing FPGA designs, resolve complex timing failures, and improve the overall compilation workflow. The role requires approximately 5–6 hours of daily overlap with the Hong Kong engineering team (start of the workday at 8:00–9:00 a.m. Kyiv time).
Responsibilities:
- Analyse failed timing paths, path delays, clock skew, and routing congestion in Quartus
- Review and optimise SDC constraints and static timing analysis results
- Refactor Verilog modules and restructure pipelines or FPGA architectures
- Resolve complex timing-closure and CDC issues
- Optimise high-speed digital interfaces
- Reduce compilation iterations and overall FPGA build time
- Document identified issues, implemented solutions, and recommended practices
Requirement:
- 3+ years of hands-on Verilog FPGA design experience
- Deep practical experience with Intel/Altera FPGA architecture
- Upper-Intermediate+ English level
Benefits:
- 20 paid vacation days per year
- 5 paid sick leaves per year (no medical documents required)
- Personalized development plan with training compensation
- English courses compensation
- Work equipment if needed (PC / laptop / monitor)
- Flat and transparent internal communication
- Opportunity to switch between projects and technologies within Digis
Principal FPGA Timing Specialist
Company:
Digis (a Fiverr company)
Location:
Worldwide
Employment type:
Fulltime
Work Arrangement:
Full Remote
Short Summary:
We are looking for a Principal FPGA Timing Specialist to analyse and optimise existing FPGA designs, resolve complex timing failures, and improve the overall compilation workflow. The role requires approximately 5–6 hours of daily overlap with the Hong Kong engineering team (start of the workday at 8:00–9:00 a.m. Kyiv time).
Responsibilities:
- Analyse failed timing paths, path delays, clock skew, and routing congestion in Quartus
- Review and optimise SDC constraints and static timing analysis results
- Refactor Verilog modules and restructure pipelines or FPGA architectures
- Resolve complex timing-closure and CDC issues
- Optimise high-speed digital interfaces
- Reduce compilation iterations and overall FPGA build time
- Document identified issues, implemented solutions, and recommended practices
Requirement:
- 3+ years of hands-on Verilog FPGA design experience
- Deep practical experience with Intel/Altera FPGA architecture
- Upper-Intermediate+ English level
Benefits:
- 20 paid vacation days per year
- 5 paid sick leaves per year (no medical documents required)
- Personalized development plan with training compensation
- English courses compensation
- Work equipment if needed (PC / laptop / monitor)
- Flat and transparent internal communication
- Opportunity to switch between projects and technologies within Digis
Languages
EN
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