Design Verification Engineer

Position:
Design Verification Engineer

Company:
Broadcom

Compensation:
The annual base salary range for this position is USD 143,800.00 to USD 230,000.00.

Location:
USA-CO Broomfield
USA-CA-San Diego-West Bernardo
USA-Colorado-Fort Collins
USA-CA San Jose Innovation Drive
USA-CA Irvine Alton Parkway Bldg 1

Employment type:
Full time

Work Arrangement:
Not specified

Short Summary:
Broadcom's ASIC Products Division is seeking an experienced verification engineer responsible for modeling and verification activities related to complex digital and mixed signal IP blocks used in ASIC developments.

Responsibilities:
- Define verification plans and environment architecture.
- Develop test cases and test bench components.
- Conduct coverage analysis and closure, and debug.
- Work with emulation and FPGA prototyping platforms.
- Lead efforts in evaluating and driving the adoption of advanced verification methodologies/flows.
- Develop functional models for block, system, and ASIC level verification.
- Collaborate closely with design teams and EDA vendors.

Requirement:
- 12+ years of experience with verification concepts and architectures for complex digital and MXS circuits.
- Experience verifying designs at the block and system levels.
- Proficient in SystemVerilog and UVM, designing verification components.
- Experience with Synopsys, Cadence, and Mentor simulations tools.
- Strong problem-solving skills and ability to work independently and in a team.
- Must have legal authorization to work in the US.

Benefits:
- Competitive and comprehensive benefits package including medical, dental, and vision plans.
- 401(K) participation with company matching.
- Employee Stock Purchase Program (ESPP).
- Paid holidays, sick leave, and vacation time.
- Discretionary annual bonus and equity awards.